Using Electron Channeling Contrast Imaging to Optimize Defect Analysis and Wafer Fabrication

Seeking enhanced performance with compound semiconductor wafer fabrication

It’s no exaggeration to say the world runs on semiconductors. From finance and medicine to transportation and defense, semiconductors are at the heart of our digital world. With each generation of semiconductor innovation delivering improved performance and energy efficiency in a smaller footprint, new applications continue to be introduced to the world at a staggering pace.

Behind the scenes, the quest to provide greater more powerful, smaller and more reliable is not without its challenges as the semiconductor industry encounters the physical boundaries of existing semiconductors. With increasing performance needs, many are looking at alternative approaches to provide technology innovation. For instance, where logic is adopting new architectures, such as Gate-all-around FETs and “More than Moore” methods, other semiconductors, such as power, photonics and radio frequency are exploring and developing compound semiconductors.

Over the last decade, interest in compound semiconductors, made up of two or more chemical elements from two or more distinct periodic table groups, such as III-V, has continued to grow. Made from wide band gap (WBG) elements, compound semiconductors feature distinctive characteristics superior to silicon (Si). These include direct energy bandgap, high breakdown electrical fields and high electron mobility. Examples include silicon-carbide (SiC), gallium-nitride (GaN), gallium-arsenide (GaAs), and indium-phosphide (InP).

Getting ahead of new wafer fabrication challenges

While offering greater performance attributes, wafer fabrication for compound semiconductor devices pose unique challenges that can impact yield and manufacturing costs. One of the key manufacturing challenges is crystalline defects that can occur during the wafer fabrication process.

Creating devices with compound semiconductors is accomplished using epitaxial growth with atoms deposited one layer at a time under controlled conditions. Epitaxial growth takes place on a substrate, such as silicon, which creates a new layer to then build the device structures on. Building device structures on the grown epitaxial layer is advantageous as the final structures contain less crystalline defects and impurities.

However, during the epitaxial growth process, there is a considerable chance that crystalline defects on the substrate can extend into the epitaxial layer due to strain caused by a lattice constant mismatch.  When this occurs, it often results in a reliability or performance failure in the device. As a result, it is critical to eliminate or reduce the presence of crystalline defects during wafer fabrication processes.

Using electron channeling contrast imaging to identify defects in semiconductors

Accomplishing defect reduction requires monitoring the occurrence, the density, and the types of crystalline defects in the grown layers and characterizing the root cause.  Unfortunately, conventional metrology methods are limited in their ability to monitor and characterize crystalline defects accurately and efficiently as they can be destructive, difficult to implement or lack the sensitivity and throughput to support wafer fabrication.

To overcome these limitations, Thermo Fisher Scientific developed a new, high-efficiency workflow using electron channeling contrast imaging (ECCI), the Thermo Scientific Apreo 2 and MAPS software. ECCI utilizes channeling contrast of back-scattered electrons to provide an optimal method for crystalline defect inspection of large areas and individual defect characterization.

Learn about electron channeling contrast imaging by watching our on-demand SPARK webinar >>

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This blog was written in collaboration between David Akerson, a senior marketing manager and Libor Strakoš, a product marketing manager at Thermo Fisher Scientific.