Semiconductor Metrology and Yield Analysis

As semiconductor device design approaches smaller nodes, it becomes more and more difficult to ramp manufacturing yields. These smaller nodes, as well as more complex 3D architectures, result in added steps and more complexity in the design process. Hundreds of steps are involved, and any defect or electrical fault that occurs in any one step will slow down the total production time. Since time-to-market and time-to-yield are both crucial for the commercial success of any new semiconductor design, metrology and inspection tools are needed to make sure each of these steps is optimized. This ensures the maximum yield can be guaranteed and maintained.

Yield analysis must be carried out as quickly and as inexpensively as possible. However, given the many steps involved in device manufacture, this can often be an extremely challenging proposition. For example, in an advanced logic device, many different measurements need to be taken, such as the finFET gate height, fin height, and sidewall angle. Performing these measurements in a cost-effective and timely manner requires advanced characterization tools designed specifically for semiconductor analysis. By using automated SEM or (S)TEM based metrology instruments, manufacturers can provide accurate and timely semiconductor inspection, lower manufacturing costs, and shorten the product development cycle.

Thermo Fisher Scientific offers a suite of next-generation products with advanced analytical capabilities for semiconductor metrology and inspection. These solutions are designed to help increase productivity in semiconductor fabrication labs by improving quality control and yield in the manufacture of logic, 3D NAND, DRAM, analog, power and display devices.

Semiconductor metrology & yield ramp workflow examples

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