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All semiconductor integrated circuits (ICs) are subject to environmental electrostatic discharge (ESD) throughout their lifecycles. Designers utilize multiple techniques to protect these sensitive electronic parts from the damage caused by an unintended ESD event. The industry has standardized methods for qualifying parts against a well-defined set of stress criteria, resulting in classifications that are then assigned to the individual parts. These classifications indicate the maximum stress that the part can experience without any latent or catastrophic failure.

Every ESD control plan is required to identify devices in your portfolio that are sensitive to ESD. To accomplish this, you need to classify the level of their sensitivity. A product’s susceptibility to ESD damage depends on its ability to either:

  • dissipate the discharge energy
  • withstand the levels of current

In the past, there were three main classifications based on three different ESD models:

Model Equivalent circuit Standard
Human body model (HBM) 100 pF @ 1.5 kΩ ANSI/ESDA-JEDEC JS-001-2011
Charge device model (CDM) 4 pF/30 pF ESD S5.3.1
Machine model (MM) 200 pF @ 0Ω ESD STM5.2

Recently, MM was eliminated as a standard test method, leaving HBM and CDM as the only ESD models used today.

Human body model

The most common model for qualifying parts is HBM. This model simulates discharge occurring between a human (e.g. a hand or finger) and a conductor (e.g. a metal rail). For this model, a 100 pF (100 x 10-12 Farad) capacitor is discharged through a 1,500 Ω resistor to simulate the waveforms generated by a human body. The typical rise time of the current pulse (ESD) through a shorting wire averages 6 ns (6 x 10-9 s) and is slower for a higher resistance load. The peak current through a 500 Ω resistor averages 463 mA for a 1,000 V pre-charge voltage.
The classifications that are assigned to parts during qualification are based on the maximum voltage stress that the part can survive with no damage (either latent or catastrophic). The following table is per ESD-STM5.1:

Class Voltage range
Class 0 < 250 V
Class 1A 250 V to < 500 V
Class 1B 500 V to < 1000 V
Class 1C 1000 V to < 2000 V
Class 2 2000 V to < 4000 V
Class 3A 4000 V to < 8000 V
Class 3B ≥ 8000 V

Charged device model

In the CDM model, it is the device itself that becomes charged; this is typically induced triboelectrically by sliding out of a tube/bag/sorter/etc. When the charged part contacts a conductor at a different potential (e.g. a tabletop, hand, or metal tool) the device will rapidly discharge to that conductor and may result in subsequent device failure. The length of the discharge may be very short (less than 1 nanosecond), but the peak current can be quite high. The CDM model uses either a 4 pF or 30 pF verification module (coin) which simulates a peak current anywhere from 2 to 30 amps. The following table is per ESD-STM5.3.1:

Class Voltage range
Class C1 < 125 V
Class C2 125 V to < 250 V
Class C3 250 V to < 500 V
Class C4 500 V to < 1000 V
Class C5 1000 V to < 1500 V
Class C6 1500 V to < 2000 V
Class C7 ≥ 2000 V

The standards committees strongly recommend that each component should be fully classified using both HBM and CDM. That means an item may be classified as both Class 2 (HBM) and Class C1 (CDM). These guidelines are typically used to:

  • Develop and measure suitable on-chip protection
  • Enable comparisons between devices (competitive)
  • Provide a system of ESD sensitivity classification to assist in the ESD design and monitoring requirements of the manufacturing and assembly environments
  • Have documented test procedures to ensure reliable and repeatable results

Please see our products page for a complete suite of test systems to help with your device qualification requirements.


ESD qualification workflow example



ESD Compliance Testing

Electrostatic discharge (ESD) can damage small features and structures in semiconductors and integrated circuits. We offer a comprehensive suite of test equipment which verifies that your devices meet targeted ESD compliance standards.

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ESD Compliance Testing

Electrostatic discharge (ESD) can damage small features and structures in semiconductors and integrated circuits. We offer a comprehensive suite of test equipment which verifies that your devices meet targeted ESD compliance standards.

Learn more ›


Semiconductor Materials and Device Characterization

As semiconductor devices shrink and become more complex, new designs and structures are needed. High-productivity 3D analysis workflows can shorten device development time, maximize yield, and ensure that devices meet the future needs of the industry.

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MK.4TE ESD and Latch-Up Test System

  • Rapid-relay-based operations—up to 2304 channels
  • Advanced device preconditioning with six separate vector drive levels
  • Fully compliant Latch-Up stimulus and device biasing

Orion3 Test System

  • Charged device model testing
  • Dual high resolution color cameras
  • Test densities to less than 0.4mm pitch

Celestron Test System

  • Wafer and package level TLP testing
  • High current TLP pulse generato
  • Can be interfaced with semiautomatic probers
  • Intuitive software for control and report generation


  • Testing per the latest industry standards
  • True system level ESD 150pF/330Ω network
  • 2 pin connection via wafer probes to any device

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Electron microscopy services for

To ensure optimal system performance, we provide you access to a world-class network of field service experts, technical support, and certified spare parts.

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