Semiconductor process development
Accelerating product development and time-to-market are critical, because missing a technology window, or falling behind, can be extremely costly. Increased density, smaller features and advanced packaging are making it more difficult to inspect, measure and test chips with confidence that initial designs will function as intended. As logic architectures have evolved from planar to FinFETs and in the future to Gate-All-Around (GAA) FETs, or nanosheets, each successive generation introduces unique and new defects. Here, we discuss semiconductor advancement through circuit editing, it’s applications and benefits and the next generation of logic.
Introducing our new Thermo Scientific Centrios HX Circuit Edit System >>
Focused ion beam circuit edit
Focused Ion Beam (FIB) chip circuit editing is a well-established technique that enables the direct repair of integrated circuit defects. A precisely tuned and placed ion beam in conjunction with process gases selectively uncovers internal circuitry, allowing a skilled FIB operator to make functional changes to the device or the copper wiring pattern. The FIB operator then reseals the chip surface to produce a device with revised circuit logic functions.
For circuit edit practitioners, the applications include:
- Exploring and validating design changes
- Prototyping new devices without costly and time-consuming mask set fabrication
- Duplicating and scaling fixes
- Debugging and optimizing devices that are already in production
For many, circuit editing provides real benefits, often quantified in terms of cost savings, productivity and time-to-market. For example; the ability to rapidly prototype lets developers proactively debug, repair and validate fixes for known issues without committing to a mask spin. The eliminates unnecessary wafer cost and schedule delays. Once the fix is verified on the prototype, it’s possible to duplicate the fix on additional devices for internal software, test, validation, and qualification teams and even customers. This last one can be especially important as it allows customers to get into production on schedule.
Circuit edit solutions for semiconductor device development
Each generation of architecture and fabrication process node advancement brings new challenges for semiconductor designers and circuit editing.
The introduction of the FinFETs with new architectural structures, multi-patterning, and unique thermal and reliability behaviors brought a fundamental change to circuit editing. Where point-to-point wiring changes were scalable on planar FETs, the thinner, dielectric layers FinFETs are more susceptible to transistor performance alterations. As a result, there is a greater need for lower landing energies to keep the beam from penetrating sensitive layers.
Additionally, for circuit editing on FinFETs, opening a window to do a CAD alignment is needed to identify the specific structure to be cut and where to make the new connection. Opening a window at 5kV versus 30kV allows the operator to open a larger window to make more structures visible for CAD alignment without risking damage to the device. At 30kV, you have to work with a very narrow window, making it hard to do CAD alignments. If you open a window prior to CAD alignment, there is a possibility of being in the wrong place and compromising the device.
Looking forward, as semiconductor manufacturers move to nanosheets, this will bring a change in the transistor architecture as well as with back-side power delivery with buried power rails. Of these, back-side power delivery with buried power rails will create a new application for circuit editing. In nanosheets with back-side power delivery, all the interconnects that deal with delivering power rather than data, are moved beneath the transistors, which require a new method for fault isolation.
With today’s FinFETs, optical tools require sample preparation for fault localization. This is accomplished by thinning the backside silicon to allow the beam to penetrate to the transistor level. For nanosheets with back-side power delivery, thinning the backside silicon will not be possible, as the power connections will be destroyed. As a result, performing fault localization on nanosheet devices will require a FIB circuit editing solution to open a window, providing the fault isolation tool with direct access to the interconnect levels. This will need to be accomplished without compromising the devices performance.
With this in mind, we’re proud to introduce our Thermo Scientific Centrios HX Circuit Edit System: a state-of-the-art solution that allows semiconductor manufacturers to optimize success rates with high resolution imaging and precise editing of today’s leading-edge devices. With its new Celta FIB column, the Centrios HX offers improved resolution, lower beam current and landing energy for intricate circuit modification without adversely affecting circuit performance or integrity. This innovation allows advanced semiconductor manufacturers and designers to achieve faster time-to-market, while minimizing mask related development costs.
With each semiconductor advancement, leading semiconductor designers have and are recognizing the strategic importance of FIB circuit edit tools to get to first silicon, optimize performance and functionality, reduce costs and mitigate program risks. As they develop the next generation of semiconductor technology, we look forward to working with them to deliver the next generation of circuit edit solutions to improve the success rates of designs.
This post was written by John Miller, a Senior Product Marketing Manager, and David Akerson, a Senior Global Market Development Manager at Thermo Fisher Scientific.