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ESD testing applications
We provide a range of equipment for electrostatic discharge (ESD) testing of microelectronics, including characterizing protection circuits, performing failure analysis, and qualification testing, to ensure compliance with industry standards.
Quality assurance through industry-standard ESD testing
One of the most critical uses of compliance testing equipment is quality assurance (QA), in which ESD and latch-up testing are performed on a new, finished device to prove that its protection circuits are functioning as expected and that it meets the required standards.
The Thermo Scientific MK.1TE, MK.2TE, and MK.4TE Test Systems are capable of performing both ESD (human body model (HBM) and machine model (MM)) and latch-up testing with precise waveforms and even high-current configurations for some models. For comprehensive standards QA, the Thermo Scientific Orion3 Charged Device Model (CDM) Tester provides charged device model (CDM) ESD testing needs.
What is latch-up testing?
Latch-up testing is testing for susceptibility when a low-impedance path develops between power rails of a CMOS device, resulting in excessive supply current consumption. Latch-up is caused by electrical overstress. The overstress can be caused by different events during operation, including voltage or current overstress on a signal pin or overvoltage on the power rail, as well as transients. The former two cases most often involve the JEDEC78 test method, which uses a square wave pulse and measures the post-stress current increase, compared to the pre-stress current.
Design validation and pre-production ESD qualification
New integrated circuit designs can be brought to production faster and with greater confidence by leveraging ESD simulation and testing equipment to determine whether their protection circuitry can withstand ESD events. Both wafers and packaged die can be tested with our comprehensive coverage of device form factors.
When should ESD tests be conducted during design?
The Thermo Scientific Celestron Test System offers transmission line pulse (TLP) testing to verify a new ESD protection structure’s design parametric characteristics, while the Thermo Scientific Pegasus Test System verifies design robustness through HBM testing, both at the wafer level. After packaging, the automated MK series of testers perform qualification to HBM and latch-up testing, while the Orion Test System verifies a device’s performance with charged device model (CDM) testing.
When design validation of both the wafer and packaging is complete, the finished product will also undergo the same QA steps as any newly manufactured device.
Failure analysis and root cause ESD investigation
When a failed part is returned with a suspected ESD failure from the field, our complete testing solutions can help to replicate and identify the root cause.
How do you perform failure analysis when ESD is suspected?
To reproduce and understand the nature of a failure, it is possible that all standards will be tested on the failed part, meaning TLP, CDM, HBM, and MM. This workflow includes the Celestron Test System, Orion Test System, and MK Series Test Systems to address each compliance test.
After the failure is better understood, in some cases, further electrical and physical testing and diagnostics and needed for complete failure analysis.
For Research Use Only. Not for use in diagnostic procedures.